The present invention generally relates to semiconductor devices, three-dimensional semiconductor devices, and methods of manufacturing semiconductor devices, and, more particularly, to a semiconductor device that is suitable for a stacked structure, a three-dimensional semiconductor device that is formed by stacking the semiconductor devices on one another, and a method of manufacturing the semiconductor device.
In recent years, three-dimensional semiconductor devices in which semiconductor devices are stacked on one another have been developed as highly-integrated, smaller semiconductor components. To produce a three-dimensional semiconductor device with higher reliability, highly reliable electric connection between the stacked semiconductor devices is essential. To achieve the highly reliable electric connection between the stacked semiconductor devices, highly reliable electrode parts formed through the substrate of each semiconductor device are essential.
Japanese Laid-Open Patent Application No. 2000-277689 discloses a semiconductor device having a three-dimensional structure.
In the formation of the semiconductor device having a three-dimensional structure disclosed in the publication, holes that penetrate not only a thinned semiconductor substrate having semiconductor devices formed thereon but also electrode pads are formed at the locations on the semiconductor substrate corresponding to the electrode pads of the semiconductor devices. After the holes are filled with resin, through holes are formed in the resin, and the through holes are filled with a conductive material to form via wiring plugs. The semiconductor substrate is then diced into semiconductor devices, thereby forming three-dimensional semiconductor chips.
The semiconductor chips are stacked on one another. Electric connection between the vertically aligned semiconductor chips is obtained by connecting the via wiring plugs to one another with soldering balls or stud bumps.
In this structure, the through holes are formed in the electrode pads, and the via wiring plugs are formed in the through holes with resin layers. Therefore, it is necessary to employ an electric connection part between each electrode pad and the corresponding via wiring plug. As a result, an increase in the connection resistance cannot be avoided between each electrode pad and the corresponding via wiring plug.
Also, having a through electrode in the middle, each of the electrode pads has a smaller area, resulting in difficulties in wire bonding and connecting with other electrodes.
Japanese Laid-Open Patent Application No. 2001-94039 discloses a structure in which semiconductor chips each having a protruding electrode formed on a principal surface are stacked up. More specifically, after the semiconductor chips are stacked up, vertical holes that penetrate the protruding electrodes and the semiconductor chips of the stacked structure are formed, and conductive members are formed in the hole with insulating layers. Also, through holes are formed under the respective protruding electrodes of the semiconductor chips each having the protruding electrode on a principal surface. Conductive members are formed in the through holes with insulating layers. The semiconductor chips having the protruding electrodes and the conductive members in the through holes are stacked up in this structure.
In this structure, the through holes are formed in the respective semiconductor chips after the protruding electrodes are formed on the surfaces of the respective semiconductor chips. Therefore, it is difficult to form the through holes, while maintaining the flatness of each semiconductor chip.
The through hole formed in each semiconductor chip has a high aspect ratio, and is vertically formed. Therefore, it is difficult to form an insulating layer and a conductive layer with sufficient thicknesses in each through hole.
Japanese Laid-Open Patent Application No. 10-223833 discloses a structure in which an insulating layer is formed on the device forming surface of a silicon substrate. More specifically, a vertical hole that penetrates the insulating layer and reaches a certain depth in the silicon substrate is formed. The hole is filled with metal, and a pad is formed over the holes. The silicon substrate is then thinned from the bottom surface, so as to expose the filling metal layer. Thus, a through plug is formed.
After the formation of the through plug, a circuit is formed on the device forming surface. Such silicon substrates are stacked up.
In this structure, the through hole formed in the semiconductor chip has a high aspect ratio, and is vertically formed. Therefore, it is difficult to form an insulating layer and a conductive layer with sufficient thicknesses in each through hole.
Japanese Laid-Open Patent Application No. 8-306724 discloses a structure in which an etching hole that reaches the non-circuit forming surface (the bottom surface) of a semiconductor chip is formed in the vicinity of an electrode pad on the circuit pattern forming surface of the semiconductor chip. The etching hole is filled with a conductive material, and an external terminal is provided on the bottom surface of the semiconductor chip. Such semiconductor chips are stacked on one another in this structure.
In this structure, each through hole is formed at a distance from each corresponding electrode pad. As a result, each semiconductor chip takes up a large area. Therefore, this structure is not suitable for high integration.
Japanese Laid-Open Patent Application No. 11-251320 discloses a structure in which a through hole is formed from the bottom surface to the upper surface of a silicon substrate. A through contact region is formed in the through hole with an insulating layer, and an electronic component formed on the upper surface of the silicon substrate is connected to the through contact region via a metal layer. Thus, the electronic component is electrically led to the bottom surface of the silicon substrate.
In this prior art, the technique of stacking up semiconductor devices is not mentioned, and the structure having a through hole in the electrode pad area of a semiconductor substrate is not suggested.
Among the conventional semiconductor devices having three-dimensional structures, each memory three-dimensional semiconductor device has a chip select unit that designates a memory semiconductor chip to perform data read and write operations among stacked memory semiconductor chips. Such a conventional memory three-dimensional semiconductor device has a chip select circuit as the chip select unit formed in each memory semiconductor chip. The chip select circuit is formed on the integrated circuit forming surface of each memory semiconductor chip. As a result, each of the memory semiconductor chips becomes larger in size, and the memory three-dimensional semiconductor device becomes larger in size on a plan view. In accordance with this prior art, it is difficult to produce a small-sized memory three-dimensional semiconductor device.